1. Field of the Invention
The present invention relates to a solid state imaging device, a driving method for the solid state imaging device, and an imaging apparatus. More specifically, the invention relates to a charge-transfer solid state imaging device represented by a CCD (charge coupled device) solid state imaging device, a driving method for the solid state imaging device, an imaging apparatus using the solid state imaging device, and an image input apparatus.
2. Description of the Related Art
A charge-transfer solid state imaging device, such as a CCD solid state imaging device, employs a method called “pinning operation” for suppressing the increase of the dark current occurring in vertical transfer registers. More specifically, the imaging apparatus employs a driving method that performs transfer driving of vertical transfer registers by using four phase-differential transfer pulse trains each having two voltage values. Of the two voltage values, one value is 0 V as the potential of the positive side (high level side) and the other value is a negative side voltage value VL as the potential of the negative side (low level side) (for example, see Japanese Unexamined Patent Application Publication (JP-A) No. 2004-328680 (such as FIG. 4 and corresponding to portions of Specification).
The JP-A No. 2004-328680 discloses a driving method for a CCD (charge coupled device), in which four phase-differential transfer pulse trains each having two voltage values respectively at the high and low levels are used to thereby perform transfer driving of vertical transfer registers.
FIGS. 1A to 1D, respectively, shows waveform diagrams of the vertical transfer pulses Vφ1 to Vφ4 as described in JP-A No. 2004-328680. In the drawing figures, a case is shown in which the high level voltage is 0[V], and the low level voltage is a negative side voltage value VL.
As shown in FIGS. 1A to 1D, the four phase-differential vertical transfer pulse trains (Vφ1 to Vφ4) for driving the vertical transfer register are composed of the vertical transfer pulses Vφ1 and Vφ2 that are each at a “normally high” level and that each have a longer high level (0[V], for example) duration than a low level (negative side voltage value VL, for example) duration, and the vertical transfer pulses Vφ3 and Vφ4 that are each at a “normally low” level and that each have a longer low level duration than a high level duration.
The “normally high” level refers to a voltage level that is high during a standby time period inclusive of a light reception time, and the “normally low” level refers to a voltage level that is low during the standby time period.
As the potential on a silicon surface functioning as a vertical charge transfer channel is brought close to the negative side, the potential on the silicon surface is reduced, and holes are likely to accumulate thereon. As such, the influence of the surface level that is caused by a defect on the silicon surface, that is, generation of electrons from the surface level, which is a dominant cause of dark current generation, is significantly suppressed. As a consequence, an increase of dark current can be suppressed. Such a phenomenon is caused by an effect called “pinning effect.”
In the event that a low level potential is applied to the transfer electrode of the vertical transfer register from the state where a high level potential is applied to the transfer electrode, a high pinning effect takes place. In the potential range therebetween, however, the pinning effect decreases as the potential is closer to the high level side and becomes higher as the potential is closer to the low level side.
According to the pinning effect, by the application of the negative voltage to the transfer electrode of the vertical transfer register from the state where 0 V is applied to the transfer electrode, an inversion layer is formed on the silicon surface, also the surface level of the vertical transfer register is filled with holes, and the amount of electrons being generated from the surface level, which is the dominant cause of dark current generation, are significantly reduced, and whereby an increase of the dark current can be suppressed. As such, the potential on the negative side of the transfer pulse for driving the vertical transfer register is very important.
In addition, Japanese Unexamined Patent Application Publication No. 2004-221339 discloses a technique for reducing noise attributed to the dark current. According to the technique, in a vertical transfer register, the number of vertical transfer electrodes (the number of storage gates), which are driven by normally high pulses respectively having a low pinning effect and a long high level duration, are reduced, thereby suppressing the occurrence of the dark current.